VLSI 8-bit Microprocessor Core
For our VLSI project, we designed a simple 8-bit microprocessor core end to end—schematic → layout → verification. The focus was building physical blocks that tile nicely, route cleanly, and pass DRC/LVS. This project was build with TSMCN65 technology.
Overview
Block diagram + instruction set
The big picture: modules + data flow, and the opcode-level behavior that drives control.
Modules we built
The core is assembled from reusable, layout-first blocks:
Floorplanning: legacy blocks and the consequences
We started by laying out the adder and shifter first. Those early layouts were much larger and less dense than the blocks we designed later—great for learning, bad for floorplanning. We originally aimed for a clean, compact floorplan, but because the adder + shifter were already committed (and physically huge), we ended up adopting a much uglier floorplan that could actually fit them.
SRAM module: extreme density, powered by pure stubbornness
The SRAM was the module we had the most fun making. We achieved extreme density after many iterations—and an unhealthy amount of ruler usage to squeeze every spacing down to the minimum that still passes DRC. We used a classic 6T bitcell sized for read/write stability. The read path is intentionally simple: precharge bit and bit_bar during clock_low, let the selected cell pull one side down during read, and then read bit_bar with an inverter. The upside is simplicity and area efficiency. The downside is that read speed is capped by how long it takes the cell to discharge a precharged node; many modern SRAMs use sense amplifiers to detect small differentials faster. For writes, we drive bit/bit_bar low according to the intended value. A highlight: we fit the read/write logic inside the SRAM bit pitch by heavy diffusion sharing and spacing optimization.
PLA design: decoder built at the end (and it shows in the density)
The PLA/control block was created near the end of the project, and it demonstrates how compact our later layouts became. We started from a truth table of control signals derived from the opcodes, used Espresso to simplify the sum-of-products, then implemented an extremely compact AND plane + OR plane. Like the SRAM, diffusion sharing and careful routing were the main weapons.
Shifter design: the legacy wide-boy
This is where the legacy design shows up. We built an 8-bit logical left shifter using 2:1 muxes in a logarithmic structure (3 layers). Each mux is implemented as a pair of transmission gates (one pMOS + one nMOS). Because pass-transistor chains can weaken signals, we added inverter restore stages for depths ≥ 2. We also intentionally made the shifter extremely wide so it could sit directly on top of the adder and respect the (already wide) bit spacing.
Adder design: first layout, still stackable
The adder was the very first layout we did, and it shows: it’s larger and less dense than our later blocks. Functionally, it’s an 8-bit ripple-carry adder built from eight full adders. Overflow is computed by XOR’ing the final carry-out with the carry-in to the MSB. Even early on, we designed with physical data flow in mind: the full-adder tile is shaped so carry chains stack cleanly, and the carry-in/out routing stays straightforward.
Remaining modules (latch, bus driver, mux) coming next—this page is being updated as we add more block deep-dives.
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