P6-Style Out-of-Order RISC-V Processor

Design Highlights

• Six-stage pipeline (IF → ID → IS → EX → CP → RT) with single-issue, out-of-order execution inspired by Intel’s P6 core.
• Register renaming via a 32-entry Map Table and a 32-entry ROB to remove WAR/WAW hazards and support precise exceptions.
• Unified 8-entry LSQ enables speculative loads and enforces memory ordering; ties into a direct-mapped, write-back, non-blocking D-cache.
• Multiple functional units—dual ALUs for branches/arithmetic plus an 8-stage pipelined multiplier; arbitration favours multiplier results.
• Misprediction recovery handled in the Retire stage; BTB/RAS predictor is future work, but full pipeline-flush logic is already in place.

Performance Snapshot

On the single-FU core we measured an average CPI of 10.3 across 30+ assembly tests (best 3.8, worst 30). Enabling the pipelined multiplier shifts the average CPI to 10.6—some programs speed up, others slow down due to extra LSQ/ROB pressure.